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part with prevention of breakthroughs of the type 'punch through

机译:防止“突破”类型突破的部分

摘要

PROBLEM TO BE SOLVED: To provide a technique for dimensionally reducing a semiconductor device with punch-throughs prevented in spite of an intra-well gap reduced to the submicron scale.;SOLUTION: On a p-type semiconductor substrate 1, a p-well 4 is sandwiched in between two n-wells 2 and 3, and a p-well 5 or a p-type epitaxial layer is provided beneath the two n-wells 2 and 3 and the p-well 4. By using this design, punch-throughs are prevented from occurring in between the two n-wells 2 and 3 and the gap between the two n-wells 2 and 3 is narrowed down.;COPYRIGHT: (C)2004,JPO&NCIPI
机译:要解决的问题:提供一种尺寸减小半导体器件的技术,尽管将阱内间隙减小到亚微米级,但仍避免了穿通现象;解决方案:在p型半导体衬底1上,p阱在两个n阱2和3之间夹有图4所示的衬底,并且在两个n阱2和3以及p阱4的下方设置有p阱5或p型外延层。防止在两个n阱2和3之间出现贯通现象,并且缩小了两个n阱2和3之间的间隙。;版权所有:(C)2004,JPO&NCIPI

著录项

  • 公开/公告号DE602004018555D1

    专利类型

  • 公开/公告日2009-02-05

    原文格式PDF

  • 申请/专利权人 NEC ELECTRONICS CORP.;

    申请/专利号DE20046018555T

  • 发明设计人 MIZUNO RIKI;KAWAGUCHI HIROSHI;

    申请日2004-01-26

  • 分类号H01L21/761;H01L27/092;H01L21/8238;

  • 国家 DE

  • 入库时间 2022-08-21 19:08:20

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