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SIMD COMPUTING UNIT, COMPUTING METHOD OF THE SIMD COMPUTING UNIT, ARITHMETIC PROCESSING UNIT, AND COMPILER

机译:SIMD计算单元,SIMD计算单元的计算方法,算术处理单元和编译器

摘要

PPROBLEM TO BE SOLVED: To execute a high-speed Dekker's algorithm in SIMD computing. PSOLUTION: The arithmetic processing unit includes: a compiler which compiles a program using addition errors; a storage means which stores a plurality of instructions from the compiler; and the computing unit which executes a plurality of operations by single command multiple data (SIMD) method based on an instruction read from the storage means. The computing unit includes a register for SIMD, which has a first register group and a second register group each of which comprises a plurality of registers; and a computing means which computes two input values input from the first register group and the second register group based on the SIMD method. The computing means includes a first computing means which compares the absolute values of the two input values and outputs the value with the larger or equal absolute value as the first value; and a second computing means which compares the absolute values of the two input values, and outputs the value with the smaller or equal absolute value as the second value, and a third computing means which executes addition and subtraction by using the first and second values. PCOPYRIGHT: (C)2010,JPO&INPIT
机译:

要解决的问题:在SIMD计算中执行高速Dekker算法。

解决方案:算术处理单元包括:编译器,其使用加法错误来编译程序;以及存储装置,其存储来自编译器的多个指令;计算单元基于从存储装置读取的指令,通过单命令多数据(SIMD)方法执行多个操作。计算单元包括用于SIMD的寄存器,其具有第一寄存器组和第二寄存器组,每个第一寄存器组和第二寄存器组均包括多个寄存器。计算装置,其基于SIMD方法计算从第一寄存器组和第二寄存器组输入的两个输入值。该计算装置包括第一计算装置,该第一计算装置将两个输入值的绝对值进行比较,并输出具有更大或相等的绝对值的值作为第一值;以及第二计算装置,其比较两个输入值的绝对值,并输出具有较小或相等的绝对值的值作为第二值;以及第三计算装置,其通过使用第一和第二值执行加法和减法。

版权:(C)2010,日本特许厅&INPIT

著录项

  • 公开/公告号JP2010049611A

    专利类型

  • 公开/公告日2010-03-04

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP20080215137

  • 发明设计人 KOBAYASHI YUSUKE;

    申请日2008-08-25

  • 分类号G06F7/50;G06F9/45;G06F9/38;

  • 国家 JP

  • 入库时间 2022-08-21 19:01:09

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