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Duty correction voltage generation circuit and duty correction voltage generation method
Duty correction voltage generation circuit and duty correction voltage generation method
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机译:占空比校正电压产生电路和占空比校正电压产生方法
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摘要
The present invention related to an apparatus and a method for increasing a voltage level of duty correction voltages to a predetermined level during a predetermined time in a delay locked loop. An apparatus, included in a delay locked loop, includes a control block for generating a control signal keeping a first logic state during the predetermined time in response to a reset signal resetting the delay locked loop; and a voltage supplier for supplying the duty correction voltage with a supply voltage during the predetermined time in the control signal, wherein the duty correction voltage is for correcting a duty cycle of a clock signal used in the delay locked loop.
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