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CPU peripheral devices for clock generation circuit and the CPU peripheral devices for clock generation method

机译:用于时钟生成电路的CPU外围设备和用于时钟生成方法的CPU外围设备

摘要

PROBLEM TO BE SOLVED: To provide a clock generating circuit and a clock generating method for a CPU peripheral device that are capable of creating the clocks and control signals best suited for writing or reading data from a CPU to the peripheral device in synchronism with control signals output from the CPU, irrespective of changes in processes, source voltages and the like.;SOLUTION: The clock generating circuit comprises a clock delaying circuit that produces a plurality of delayed clocks in accordance with the clocks supplied to the CPU; a selective computing circuit that performs computations to determine which of the plurality of delayed clocks is to be selected on the basis of the leading or trailing edge of a write enable signal outputted from the CPU; a clock selecting circuit for selecting two or more of the plurality of delayed clocks on the basis of the output result of the selective computing circuit; and a clock computing circuit that performs computations on the two or more clocks selected. The clocks and the write enable signal output from the clock computing circuit are used respectively as operating clocks and a write enable signal for the CPU peripheral device.;COPYRIGHT: (C)2006,JPO&NCIPI
机译:解决的问题:提供一种用于CPU外围设备的时钟生成电路和时钟生成方法,其能够创建最适合与控制信号同步地从CPU向外围设备写入数据或从外围设备读取数据的时钟和控制信号。解决方案:时钟产生电路包括时钟延迟电路,该时钟延迟电路根据提供给CPU的时钟产生多个延迟的时钟。选择性计算电路,其基于从CPU输出的写使能信号的上升沿或下降沿执行计算以确定要选择多个延迟时钟中的哪个时钟;时钟选择电路,用于根据选择运算电路的输出结果,选择多个延迟时钟中的两个以上。时钟计算电路对所选择的两个或多个时钟进行计算。从时钟计算电路输出的时钟和写使能信号分别用作CPU外围设备的工作时钟和写使能信号。版权所有:(C)2006,JPO&NCIPI

著录项

  • 公开/公告号JP4518855B2

    专利类型

  • 公开/公告日2010-08-04

    原文格式PDF

  • 申请/专利权人 株式会社リコー;

    申请/专利号JP20040216178

  • 发明设计人 道吉 啓;

    申请日2004-07-23

  • 分类号G06F1/10;G06F1/12;

  • 国家 JP

  • 入库时间 2022-08-21 18:58:19

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