The global bus synchronous transaction acknowledgment which has unanswered detection

摘要

An integrated multi-processor system with clusters (130, 131, 132 and 133) of processors (25) ON a high speed split transaction bus (16) uses a transaction acknowledge (TACK), by a target device in response to receiving a request from a master device ON the bus. The master and target devices connect to the bus via a global bus interface (17; 31B and 33B) with FIFO registers (31A and 33A) acting as buffers and the target interface includes a TACK generator (Fig. 6) that flips the state of the global bus' TACK line (TACK#) upon determining that a broadcast request is addressed to its target device. A bus idle default device (BIDD) (18; Fig. 8) generates a TACK signal when no device is ON the bus and also detects the absence of any TACK response (165) by monitoring the state of the TACK line and thereby indicating that a master device attempted to address a nonexistent target device. The BIDD then generates a dummy response for the requesting master device with data flags set to invalid data.