CPU DATA BUS PLD/FPGA INTERFACE USING DUAL PORT RAM STRUCTURE BUILT IN PLD

摘要

A programmable logic device and a system and method using the programmable logic device are disclosed. The programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. The system may include the programmable logic device in data communication with a central processing unit and a controller. The method may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address.