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TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS
TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS
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机译:婴儿死亡率相关缺陷的测试电路和方法
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摘要
The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.
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