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Signaling with Superimposed Differential-Mode and Common-Mode Signals

机译:叠加差分模式和共模信号的信令

摘要

A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,—the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
机译:数据接收器电路( 206 )包括耦合到第一和第二各自的传输线( 204 )的第一和第二接口( 221 )。第一和第二各自的传输线包括在数据接收器电路外部的一对传输线。第一和第二接口从该对传输线接收传输信号。共模提取电路( 228 )耦合到第一和第二接口,以从接收到的传输信号中提取共模时钟信号。差模电路( 238 )耦合到第一和第二接口,以从接收的传输信号中提取差模数据信号。提取的数据信号具有与提取的时钟信号的频率相对应的符号率(例如,-符号率可以是提取的时钟信号的频率的两倍)。差分模式电路与提取的时钟信号同步。

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