METHOD FOR CLOCK JITTER STRESS MARGINING OF HIGH SPEED INTERFACES

摘要

A method for clock jitter stress margining of high speed interfaces including generating a jittered clock signal via a clock signal generator of a high speed interface controller card, inputting the jittered clock signal to a control input of a looped-back port of the high speed interface controller card, inputting a test pattern signal to the looped-back port generated from a logic circuitry of the high speed interface controller card, receiving the test pattern signal to the logic circuitry from the looped-back port via the transmitter to the receiver, monitoring a bit error rate of the looped-back port by comparing the received test pattern signal to the inputted test pattern signal, and outputting a fail indication signal if the bit error rate is within a fail threshold.