首页> 外国专利> VARIATION AWARE VICTIM AND AGGRESSOR TIMING OVERLAP DETECTION BY PESSIMISM REDUCTION BASED ON RELATIVE POSITIONS OF TIMING WINDOWS

VARIATION AWARE VICTIM AND AGGRESSOR TIMING OVERLAP DETECTION BY PESSIMISM REDUCTION BASED ON RELATIVE POSITIONS OF TIMING WINDOWS

机译:基于定时窗口相对位置的PESSIMIST减少法的变态预警受害者和定时重叠检测

摘要

A computer is programmed to identify a number of groups of timing windows, each group including a victim timing window and one (or more) aggressor timing window(s), respectively for a victim net and one (or more) aggressor nets in an IC design. The computer automatically slides (i.e. shifts in time) the victim and aggressor timing windows as a group for each die, i.e. by a specific amount that is identical for all timing windows of an instance of a coupled stage in a die, but differs for other instances of the same coupled stage in other dies. Crosstalk analysis is then performed, using time-shifted timing windows which result from sliding, to identify overlapping victim and aggressor nets, followed by variation aware delay calculations to identify timing violations and timing critical nets, followed by revision of the IC design, which is eventually fabricated in a wafer of semiconductor material.
机译:对计算机进行编程以识别多个定时窗口组,每组定时窗口分别包括一个受害者定时窗口和一个(或多个)攻击者定时窗口,分别用于IC中的一个受害者网络和一个(或多个)攻击者网络。设计。对于每个骰子,计算机会自动将受害者和侵害者定时窗口作为一组滑动(即,在时间上移动),即,一个特定的数量对于一个骰子中耦合阶段的实例的所有定时窗口都是相同的,而对于其他骰子则有所不同其他模具中相同耦合阶段的实例。然后进行串扰分析,使用滑动产生的时移时序窗口,以识别重叠的受害方网络和侵害方网络,然后进行变化感知延迟计算,以识别时序违规和时序关键网络,然后修改IC设计,即最终制造在半导体材料的晶圆中。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号