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Enhancing Formal Design Verification By Reusing Previous Results
Enhancing Formal Design Verification By Reusing Previous Results
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机译:通过重用以前的结果来增强形式设计验证
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摘要
A method, a system and a computer program product for re-using verification results associated with a circuit design to eliminate a formal verification re-run associated with a subsequent verification of the circuit design. A Verification Data Re-use (VDR) utility initiates the creation of a first netlist data structure and a first set of target signatures for the circuit design. The VDR utility initiates an initial functional verification run of the circuit design and stores the results of the verification run. When a subsequent verification of the initial design is initiated, the VDR utility compares the first set of target signatures with a second set of target signatures for the subsequent verification run. A match of target signatures indicates that corresponding design targets have an identical functionality and the VDR utility re-uses verification results from the initial verification run to eliminate an extensive formal verification
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