CORRELATION AND OVERLAY OF LARGE DESIGN PHYSICAL PARTITIONS AND EMBEDDED MACROS TO DETECT IN-LINE DEFECTS

摘要

A method of identifying defects in a chip integral to a wafer by correlating physical defects to a corresponding logic fail. The method includes partitioning a logic representation of the chip; identifying physical defects and determining corresponding coordinates of each identified physical defect; determining boundaries of the failing logic partitions, each logic partition being bound by coordinates; and correlating the physical coordinates of the defects to the bounded failing logic partitions. The scaled back, low overhead method correlates design sensitivities and test fails to physical process defects detected during semiconductor manufacturing in-line test inspection. It further identifies and records design physical coordinates of large embedded logic physical partitions test structures, memory arrays, and the like.