首页> 外国专利> Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits

Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits

机译:指定的MOSFET和驱动器设计可实现分立电路中的最低寄生

摘要

Apparatus are described for a pair of MOSFET power transistors, a MOSFET driver, and an idealized circuit layout utilized in a power stage such as that of a power conversion system. The power stage comprises a pair of MOSFET transistors having substantially identical electrical characteristics and complementary package configurations for simplifying and optimizing the layout of the power stage on a single side or layer of a printed circuit board. The ideal layout effectively avoids parasitic circuit components, minimizes layout area and costs, and permits operation at higher switching frequencies. A new MOSFET transistor pin configuration is also described that is essentially a functional mirror or functional complement of an existing MOSFET transistor pin configuration to provide the complementary package configurations and the optimized PCB layout. A customized MOSFET driver pin configuration further optimizes the power stage layout by arranging the pins of the driver to coordinate with those of the MOSFET transistor pair.
机译:描述了用于诸如功率转换系统的功率级的一对MOSFET功率晶体管,MOSFET驱动器以及理想化的电路布局的设备。功率级包括一对具有基本上相同的电气特性和互补封装配置的MOSFET晶体管,用于简化和优化功率级在印刷电路板单面或单层上的布局。理想的布局有效地避免了寄生电路组件,最小化了布局面积和成本,并允许在更高的开关频率下工作。还介绍了一种新的MOSFET晶体管引脚配置,该配置本质上是现有MOSFET晶体管引脚配置的功能镜像或功能补充,以提供互补的封装配置和优化的PCB布局。定制的MOSFET驱动器引脚配置通过将驱动器的引脚布置为与MOSFET晶体管对的引脚协调,进一步优化了功率级布局。

著录项

  • 公开/公告号US7721232B2

    专利类型

  • 公开/公告日2010-05-18

    原文格式PDF

  • 申请/专利权人 JENS EJURY;

    申请/专利号US20040998471

  • 发明设计人 JENS EJURY;

    申请日2004-11-29

  • 分类号H03F3/38;

  • 国家 US

  • 入库时间 2022-08-21 18:50:45

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号