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Watermarking a chip design based on frequency of geometric structures

机译:基于几何结构频率对芯片设计加水印

摘要

A method for watermarking a circuit design layout based on frequency or number of geometric structures. The method includes dividing a circuit design layout into a plurality of segments or tiles. Certain segments are selected, and within these selected segments, a router alters the number of geometric structures, such as vias and jogs, of the circuit design layout in the selected segments to form the watermark without relying on a netlist. The number of geometric structures is changed slightly so that a random sampling of segments would not identify the watermark since the variations would not be detectable or would be within acceptable variances, but the watermark would be readily identified if the selected segments are known. The watermark or portions thereof can be used to encode one or more data bits.
机译:一种基于几何结构的频率或数量为电路设计布局加水印的方法。该方法包括将电路设计布局划分为多个段或瓦片。选择某些段,并且在这些所选段中,路由器改变所选段中电路设计布局的几何结构(例如通孔和点焊)的数量以形成水印,而无需依赖网表。几何结构的数量略有变化,以使分段的随机采样不会识别出水印,因为这种变化将不可检测或在可接受的方差之内,但是如果已知选定的分段,则很容易识别出水印。水印或其部分可用于编码一个或多个数据位。

著录项

  • 公开/公告号US7801325B1

    专利类型

  • 公开/公告日2010-09-21

    原文格式PDF

  • 申请/专利权人 ASMUS HETZEL;IVAN Q. PEYROT;

    申请/专利号US20060478290

  • 发明设计人 ASMUS HETZEL;IVAN Q. PEYROT;

    申请日2006-06-29

  • 分类号G06K9;H04L9/32;

  • 国家 US

  • 入库时间 2022-08-21 18:50:27

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