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Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density

机译:包括具有不同电荷陷阱表面密度的电荷累积层的半导体器件及其制造方法

摘要

There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor 6 is formed through a laminate insulating film including a first gate insulating film 3, a charge accumulation layer 4 and a second gate insulating film 5 on a silicon substrate 1. The laminate insulating film (3 to 5) projects outside the gate conductor 6 and extends to under the outer end of a side wall 8. The charge accumulation layer 4 includes a high trap surface-density region 4a immediately under the gate conductor and a low trap surface-density region 4b outside the gate conductor.
机译:提供了一种陷阱存储装置,其抑制电荷从外部流入电荷累积区域,并且抑制累积的电荷由于缺陷而扩散到外部或流出。栅导体 6 通过包括第一栅绝缘膜 3 ,电荷累积层 4 和第二栅绝缘的层压绝缘膜形成。膜 5 在硅基板 1 上。层压绝缘膜( 3 5 )突出到栅极导体 6 的外部,并延伸到侧壁的外端下方8 。电荷积累层 4 包括位于栅导体正下方的高陷阱表面密度区域 4 a 和低陷阱表面密度区域 4 b

著录项

  • 公开/公告号US7791129B2

    专利类型

  • 公开/公告日2010-09-07

    原文格式PDF

  • 申请/专利权人 MASAYUKI TERAI;

    申请/专利号US20070162224

  • 发明设计人 MASAYUKI TERAI;

    申请日2007-01-18

  • 分类号H01L21/8238;H01L21/336;H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119;

  • 国家 US

  • 入库时间 2022-08-21 18:48:37

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