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Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction

机译:PLL线性度测量,PLL输出占空比测量和占空比校正的系统和方法

摘要

Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.
机译:用于实现锁相环电路(PLL)中压控振荡器(VCO)线性度确定,占空比确定和占空比校正的系统和方法。一个实施例包括一种方法,该方法包括以下步骤:确定PLL的VCO的频率响应为占空比的函数,将基于VCO输出的信号施加到VCO输入,测量VCO输出信号的最终频率,确定与测量频率相对应的占空比,并配置占空比校正单元以校正占空比VCO输出信号的50%左右。对于0%至100%之间的几个不同的占空比值中的每个,确定VCO的频率响应可以包括将VCO输入信号施加到VCO并确定VCO输出信号的对应频率。对于占空比为0%和100%的情况也可以这样做。

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