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MEMORY ARCHITECTURE FOR POSTIORIOR MAXIMUM PROBABILITY DECODER.
MEMORY ARCHITECTURE FOR POSTIORIOR MAXIMUM PROBABILITY DECODER.
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机译:最早最大概率解码器的内存架构。
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摘要
A system for carrying out a decoding of the maximum posterior probability in a scrollable window, hereinafter referred to as MAP, the decoding comprising: a) a channel deinterlacing RAM (160) for storing a block of symbol estimates; b) a total of S calculators (272, 274) of state metrics, each state metric calculator being to generate a set of state metric calculations, in which said state metric calculators (272, 274) process data in windows equal to or smaller than the size of a window RAM; c) a set of S + 1 window RAM (230A-D), in which S of said S + 1 window RAM provide symbol estimates to said S state metric calculators, and a remaining window RAM receives estimates of symbols from said channel deinterlacing RAM (160).
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