Low-power microprocessor cache memory and method for its operation

摘要

The present invention relates to a technique for processing a transmission in a communication (e.g., CDMA) system including the use of a digital signal processor. A digital signal processor includes a cache memory system, and combined with a plurality of addressable memory lines of an addressable memory, the cache memory match lines. Each of the cache memory match lines is associated with a corresponding one of the cache memory set. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory to retrieve data from a selected one of the corresponding sets of the cache memory, and drives one of the match line drive circuit is a cache memory match lines to a higher voltage at a lower voltage. Cache memory match lines from a selected one corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor is compared to the one of the addressable memory lines associated to the selected one of the cache memory match lines. After the comparison step, the process is returned to one of the cache memory match lines at a low voltage.