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FUSE SET FOR GENERATING A FUSE SIGNAL WHICH IS ENABLED ACCORDING TO THE STATE OF FUSE CUT AFTER ACTIVATION OF POWER-UP SIGNAL, AND A TEST MODE SIGNAL GENERATION CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE USING THE SAME
FUSE SET FOR GENERATING A FUSE SIGNAL WHICH IS ENABLED ACCORDING TO THE STATE OF FUSE CUT AFTER ACTIVATION OF POWER-UP SIGNAL, AND A TEST MODE SIGNAL GENERATION CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE USING THE SAME
PURPOSE: A fuse set and a test mode signal generation circuit for a semiconductor memory device using the same are provided to prevent the semiconductor memory device from entering abnormally into a test mode by disabling fuse signal before the activation of power up signal and enabling fuse signal according to the state of fuse cut after the activation of power up signal.;CONSTITUTION: Power up signal is input into a switching part(110) and the switching part outputs signal which swings between an external voltage and a ground voltage. A fuse part(120) determines whether the external voltage is applied to the switching part. A latch part(130) latches the output of the switching part. A delay part(140) delays the power up signal. Outputs from the latch part and the delay part is input into a signal combination part(150) and the signl combination part generates a fuse signal.;COPYRIGHT KIPO 2010
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