DISPLAY DRIVING SYSTEM USING SINGLE LEVEL SIGNAL TRANSMISSION WITH EMBEDDED CLOCK SIGNAL CAPABLE OF MINIMIZING IMPEDANCE MISMATCHING AND ELECTROMAGNETIC INTERFERENCE

摘要

PURPOSE: A display driving system using a single level signal transmission with embedded clock signal is provided to maximize data transmission speed, minimize a level of transmitted signal and a frequency of an embedded clock signal, and minimize the impedance mismatch and the electromagnetic wave interference.;CONSTITUTION: An LVDS(Low Voltage Differential Signaling) receiver(110) receives a data signal. A data processor(120) temporarily saves data signal. Data is processed and outputted. A timing generator(130) generates a clock signal and a timing control signal. A timing controller(100) comprises a transmitter transmitting the data signal. A low driver successively injects a gate signal on a display panel. A panel driving part receives a signal through a signal line from a transmission unit.;COPYRIGHT KIPO 2010