INNER CLOCK GENERATION CIRCUIT WHICH IS STEADILY CREATED INTERNAL CLOCK SIGNAL USING PRIMARY CLOCK SIGNAL AND SUB-CLOCK SIGNAL

摘要

PURPOSE: An inner clock generation circuit is implementing operation without the change of circuit according to the clock signal of the wide bandwidth by being steadily created the internal clock signal.;CONSTITUTION: A clock epoch detection unit(300) detects the cycle of the clock signal. A control pulse signal generating unit(400) controls the delay-value delaying the primary clock signal in response to the output signal of the clock epoch detection unit. The control pulse signal having the control pulse signal generating unit is the activation range as much as delay-value is created.;COPYRIGHT KIPO 2010