MULTI-PHASE CLOCK GENERATING CIRCUITRY CAPABLE OF IMPROVING A QUALITY AND A TRANSFER EFFICIENCY OF DATA BY REVISING A PHASE ERROR BETWEEN CLOCKS, AND A CONTROL METHOD THEREOF

摘要

PURPOSE: A multi-phase clock generating circuitry and a control method thereof are provided to generate a phase-corrected the multi-phase clock having a center phase between clocks using a phase error information between clocks.;CONSTITUTION: A phase correction block(200) receives multi-phase clocks having different phases. The phase correction block generates one or more a phase clock group interpolated. A cluck control block(500) selectively outputs one group among the phase group of the interpolated phase clock using a digital control signals of a multiple-bit created by a phase difference of the multi-phase clock. The cluck control block offers an outputting multi-clock by selectively outputting the phase group of the interpolated phase clock. The phase correction block includes a plurality of phase interpolation blocks.;COPYRIGHT KIPO 2010