首页> 外国专利> SEMICONDUCTOR DEVICE WHICH HAS A DUMMY CELL BIT LINE STRUCTURE BLOCKING A LEAKAGE CURRENT WHICH IS APPLIED TO A CELL ARRAY, CAPABLE OF PREVENTING DYNAMIC REFRESH FAULT, AND A FORMING METHOD THEREOF

SEMICONDUCTOR DEVICE WHICH HAS A DUMMY CELL BIT LINE STRUCTURE BLOCKING A LEAKAGE CURRENT WHICH IS APPLIED TO A CELL ARRAY, CAPABLE OF PREVENTING DYNAMIC REFRESH FAULT, AND A FORMING METHOD THEREOF

机译:具有虚拟细胞位线结构的半导体器件,该结构阻止了应用于电池阵列,能够防止动态刷新故障的泄漏电流及其形成方法

摘要

PURPOSE: A semiconductor device and a forming method thereof are provided to block a leakage current which is coming out from a peripheral circuit region by forming a terminal capturing a well bias in a dummy cell array bit line.;CONSTITUTION: An active area and an inactive area are formed in the memory cell area(D) and dummy cell region(C) of a semiconductor substrate(100). A gate electrode is formed in the memory cell area and the active area of the dummy cell area. An inter-layer insulating film(130) is formed on the gate electrode, the memory cell area, and the dummy cell area. A bit line plug(135) is formed on the inter-layer insulating film. The bit line is formed on the bit line plug.;COPYRIGHT KIPO 2010
机译:目的:提供一种半导体器件及其形成方法,以通过在虚设单元阵列位线中形成捕获阱偏压的端子来阻止从外围电路区域流出的泄漏电流。组成:有源区和有源区在半导体衬底(100)的存储单元区域(D)和伪单元区域(C)中形成非活性区域。在存储单元区域和伪单元区域的有源区域中形成栅电极。在栅电极,存储单元区域和虚设单元区域上形成层间绝缘膜(130)。在层间绝缘膜上形成位线插头(135)。位线插头上形成位线。; COPYRIGHT KIPO 2010

著录项

  • 公开/公告号KR20100071211A

    专利类型

  • 公开/公告日2010-06-29

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20080129844

  • 发明设计人 IM GYEONG SUB;KIM SEUG GYU;

    申请日2008-12-19

  • 分类号H01L27/108;H01L21/8242;H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 18:32:29

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