METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, CAPABLE OF UNIFORMLY PLANARIZING AN INTERLAYER INSULATION LAYER ON A MEMORY CELL REGION, A DUMMY REGION, AND A PERIPHERAL CIRCUIT REGION

摘要

PURPOSE: A method for manufacturing a semiconductor device is provided to improve planarization by preventing the difference of an etching speed on each region according to the density of a contact plug.;CONSTITUTION: Gate electrodes(110a,110b,110c) including a gate conductive pattern and capping patterns are formed on the memory cell region and the peripheral regions. A first contact hole and a second contact hole are formed by patterning the interlayer insulation layer. The bottom of the second contact hole is separated from the upper side of the gate conductive pattern. A first plug conductive layer(142a) is buried in the first contact hole. A second plug conductive layer is buried in the second contact hole. The first contact plug and the second contact plug are formed by exposing the capping patterns.;COPYRIGHT KIPO 2011