首页> 外国专利> An integrated clock supply module for a memory module memory module, comprising the integrated clock supply component comprising, as well as a method for the operation of the memory module under test conditions

An integrated clock supply module for a memory module memory module, comprising the integrated clock supply component comprising, as well as a method for the operation of the memory module under test conditions

机译:用于存储器模块存储器模块的集成时钟供应模块,包括集成时钟供应组件,该集成时钟供应组件包括:以及在测试条件下用于存储模块的操作的方法

摘要

An integrated clock supply module (1) for a memory module,with a clock signal input (1.1) for applying a first clock signal (clk1) and a clock signal output (1.2 – 1.5),with a phase-locked loop (2), which on the input side to the clock signal input (1.1) is connected and for the generation of a second clock signal (clk2) serves,by means of a multiplexer (mux), via which the first clock signal (clk1) or the second clock signal (clk2) on the clock signal output (1.2, 1.5) is switchable,with a unit for frequency monitoring (3), which on the input side to the clock signal input (1.1) is connected and which is constructed and operated in such a way that, in the case of falling below a limit frequency (fmin) of the multiplexer (mux) is caused to the first clock signal (clk1) on the clock signal output (1.2, 1.5) to switch.
机译:用于存储模块的集成时钟供应模块(1),具有用于施加第一时钟信号(clk1)的时钟信号输入(1.1)和具有锁相环(2)的时钟信号输出(1.2 – 1.5)在多路复用器(mux)的作用下,它在时钟信号输入(1.1)的输入侧连接并用于生成第二时钟信号(clk2),第一时钟信号(clk1)或时钟信号输出(1.2,1.5)上的第二时钟信号(clk2)可切换,带有用于频率监视的单元(3),该单元在时钟信号输入(1.1)的输入侧已连接并已构造和运行以这种方式,在低于多路复用器(mux)的极限频率(fmin)的情况下,对时钟信号输出(1.2、1.5)上的第一时钟信号(clk1)进行切换。

著录项

  • 公开/公告号DE10330593B4

    专利类型

  • 公开/公告日2010-11-04

    原文格式PDF

  • 申请/专利权人

    申请/专利号DE2003130593

  • 发明设计人

    申请日2003-07-07

  • 分类号G11C29/24;G11C29/00;G11C11/4076;

  • 国家 DE

  • 入库时间 2022-08-21 18:29:10

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