A process for the preparation of a dram - memory cell configuration with trench capacitors and the web field effect transistors (finfet) as well as dram - memory cell configuration

摘要

A method for producing an arrangement of the dram - memory cells (2) with a rib field effect transistors as selection transistors (4), wherein the– in a semiconductor substrate (1) in cells of lines (63) and arranged in each case to hole trenches (30) oriented trench capacitors (3) are formed, where the trench capacitors (3) of adjacent cells lines (63) are provided offset relative to one another,– between the cells lines (63) trench insulator structures (61 '') are introduced, wherein between each two in a cell row (63) adjacent trench capacitors (3) from the semiconductor substrate (1) half conductor webs (43) of the web field effect transistors (4) are formed,– a mask (8) with a respective one of the hole trenches (30) adjusted mask portions (8 '', 8 ", 8"'') is provided, wherein said mask portions (8 '', 8 ", 8"'') in each case a at the respective hole (30) subsequent section of the trench insulator structures (61 '') is covered and sections of the trench insulator structures (61'') on the respective hole (30) opposite side of the respective trench insulator structure (61 '') are not covered,– with the use of the mask (8) gate trenches (67) in the trench insulator structures (61 '') is introduced..