Pyramidal circuit grid for processing information flows, has circuit elements with outlets interconnected to inlet so that information flow in grid with planes around bit is reduced than information flow at outlets on planes for regulation

摘要

The circuit grid has an arrangement of electrical circuit elements (SQS1.1, SQS2.1, SQS3.2-SQS5.2, SQS6.3) at nodes of the grid, where the circuit elements have an inlet (P) and two outlets. A control signal is not transmitted over the outlets so that the signal flows reduced around a binary unit lie at the outlets of the circuit elements. The outlets are interconnected to the inlet of the circuit elements at next highest plane so that an information flow (IA) in the grid with planes around a bit is reduced than an information flow (IB) at the outlets on the planes for regulation.