EXPENDITURE FOR HIGH SPANISH HEADS

摘要

Circuit comprising a signal input ( 11 ) for receiving an input signal (s(t)) and a digital output stage ( 15 ) being designed for operation at a supply voltage (VSUBDD/SUB). The output stage ( 15 ) comprises a series of two n-channel CMOS transistors (no 1 , no 2 ), a common node ( 17 ) between the two n-channel CMOS transistors (no 1 , no 2 ), and an output port ( 16 ). Active voltage limiting means ( 14 ) are arranged between the signal input ( 11 ) and the common node ( 17 ) for limiting voltages (VSUBNM/SUB) at the common node ( 17 ) to a voltage limit (VSUBmax/SUB). The voltage limiting means ( 14 ) are controllable byte state of the input signal (s(t)).