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Asynchronous circuit insensitive to the delay with insertion circuit time limit

机译:异步电路对带有插入电路时间限制的延迟不敏感

摘要

The asynchronous circuit insensitive to the periods comprises at least one circuit for the insertion of time on the path of propagation of a signal. The insertion of the delay circuit comprises, between an input (5) and an output (sd) of the signal, a door by muller (5) and a plurality of delay circuits (d1. dn) connected in series with an output of the door by muller (5). The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit (7, 8, 15) having an output constitutes the output of the insertion circuit period. The door by muller (5) comprises an input connected to the output of the last time delay circuit (dn), by means of an inverting gate (6), and an input constituting the input of the signal in the insertion circuit period. The control circuit (8) of multiplexing preferably includes a random generator.
机译:对周期不敏感的异步电路包括至少一个电路,用于在信号的传播路径上插入时间。延迟电路的插入包括在信号的输入(5)和输出(sd)之间的穆勒门(5)和与延迟器的输出串联连接的多个延迟电路(d1.dn)。穆勒(5)的门。延迟电路的输出连接到复用电路(7、8、15)的相应输入,该复用电路的输出构成插入电路周期的输出。穆勒门(5)包括通过反相门(6)连接到最后时间延迟电路(dn)的输出的输入,以及构成插入电路周期中的信号输入的输入。复用的控制电路(8)优选地包括随机发生器。

著录项

  • 公开/公告号FR2932336B1

    专利类型

  • 公开/公告日2010-06-18

    原文格式PDF

  • 申请/专利权人 TIEMPO;

    申请/专利号FR20080003165

  • 发明设计人 GHISLAIN BOUESSE;MARC RENAUDIN;

    申请日2008-06-06

  • 分类号H03K5/13;H03M13/00;

  • 国家 FR

  • 入库时间 2022-08-21 18:26:46

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