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CIRCUIT SIMULATION DEVICE AND TRANSIENT ANALYSIS METHOD

机译:电路仿真装置及暂态分析方法

摘要

PPROBLEM TO BE SOLVED: To solve such a problem that a calculation amount in transient analysis of a circuit cannot be reduced when a signal always varied at a high speed such as a clock signal is used as an input signal of the circuit. PSOLUTION: A storage part 1 stores a net list showing a test target circuit. An extracting part 3 extracts a sub net list showing a cycle circuit included in the test target circuit and outputting a cycle output signal in accordance with a cycle input signal from the net list stored in the storage part 1. An analysis part 4 executes transient analysis of the cycle circuit shown by the sub net list extracted by the extracting part 3 for one cycle of the cycle output signal output by the cycle circuit. A simulation part 5 executes transient analysis of the test target circuit shown by the net list stored in the storage part 1 based on the analysis result of the analysis part 4. PCOPYRIGHT: (C)2011,JPO&INPIT
机译:

要解决的问题:为了解决这样的问题,即当始终以高速变化的信号(例如时钟信号)用作电路的输入信号时,不能减少电路的瞬态分析中的计算量。

解决方案:存储部分1存储一个显示测试目标电路的网表。提取部3从存储在存储部1中的网表中提取表示测试对象电路所包含的周期电路的子网表,并根据周期输入信号输出周期输出信号。分析部4进行瞬态分析。对于由周期电路输出的周期输出信号的一个周期,由提取部分3提取的子网列表所示出的周期电路的周期。仿真部5基于分析部4的分析结果,对存储在存储部1中的网表所示的测试对象电路进行瞬态分析。

COPYRIGHT:(C)2011,JPO&INPIT

著录项

  • 公开/公告号JP2011129029A

    专利类型

  • 公开/公告日2011-06-30

    原文格式PDF

  • 申请/专利权人 ELPIDA MEMORY INC;

    申请/专利号JP20090288984

  • 发明设计人 YAMADA JUNJI;

    申请日2009-12-21

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 18:22:26

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