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Equalizer characteristic optimization method, a transmission system, a communication apparatus and program

机译:均衡器特性优化方法,传输系统,通信设备和程序

摘要

2nd latch stage and with the logical value which is obtained at 1st latch stage and the logical value which is obtained at the aforementioned 2nd latch stage compare logical value relative stage and the setting of quality of the equalizer which latch the reception signal with 1st latch stage and the sampling clock timing which latch the reception signal with sampling clock acquisition stage and the recovery clock timing which obtain the recovery clock acquisition stage which obtains recovery clock timing from the ripple mark of the reception signal and the specified sampling clock timing which centers recovery clock timing to modify, in state after the changing the aforementioned recovery clock acquisition stage, the sampling clockIt is the constitution which consists of with the optimum setting extraction stage which calculates the setting of optimum quality of the aforementioned equalizer acquisition stage, 1st latch stage, on the basis of the data of the logical value relative result which was collected at data acquisition stage and the data acquisition stage which repeat the operation which does 2nd latch stage and logical value relative stage.
机译:将第二锁存器级与在第一锁存器级获得的逻辑值和在上述第二锁存器级获得的逻辑值比较逻辑值相对级和利用第一锁存器级锁存接收信号的均衡器的质量设置通过采样时钟获取级锁存接收信号的采样时钟定时和恢复时钟定时,获得恢复时钟获取级,该恢复时钟获取级从接收信号的波纹标记和以恢复时钟为中心的指定采样时钟定时中获得恢复时钟定时。在改变上述恢复时钟获取级之后的状态下,改变采样时钟的定时是由最优设置提取级构成的,该最优设置提取级计算上述均衡器获取级,第一锁存级的最优质量的设置。逻辑值相对结果的数据基础在数据获取阶段和数据获取阶段收集的t重复执行第二锁存阶段和逻辑值相对阶段的操作。

著录项

  • 公开/公告号JP4796645B2

    专利类型

  • 公开/公告日2011-10-19

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20090506154

  • 发明设计人 山▲崎▼ 学;登坂 正喜;

    申请日2007-03-27

  • 分类号H04B3/06;H04L25/02;H04L25/03;

  • 国家 JP

  • 入库时间 2022-08-21 18:22:28

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