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Second chance substitution mechanism for the cache-memory whose of the processor asoshieteibitei is high very
Second chance substitution mechanism for the cache-memory whose of the processor asoshieteibitei is high very
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机译:处理器asoshieteibitei很高的高速缓存的第二次机会替换机制
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摘要
The cache-memory system has, cache-memory (269,16A, 17A and 18A) with the block substitution controller (266) with. The aforementioned cache-memory can have the plural sets where each one has plural block locations. The aforementioned block substitution controller can keep the individual count value which corresponds to each set of the aforementioned cache-memory. The aforementioned individual count value is while the aforementioned specified setting, qualified block location in order to remember the substitution data is pointed. It can keep the recent access bit where as for the aforementioned block substitution controller, that the block location which corresponds recently is accessed the aforementioned block location part vis-a-vis at least respectively, shows high and is related how. In addition, the aforementioned block substitution controller, whether or not the recent access bit of specification, has shown the fact that the aforementioned qualified block location is recently accessed, can remember the aforementioned substitution data in the qualified block location which the aforementioned individual count value has pointed according to.
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