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Second chance substitution mechanism for the cache-memory whose of the processor asoshieteibitei is high very

机译:处理器asoshieteibitei很高的高速缓存的第二次机会替换机制

摘要

The cache-memory system has, cache-memory (269,16A, 17A and 18A) with the block substitution controller (266) with. The aforementioned cache-memory can have the plural sets where each one has plural block locations. The aforementioned block substitution controller can keep the individual count value which corresponds to each set of the aforementioned cache-memory. The aforementioned individual count value is while the aforementioned specified setting, qualified block location in order to remember the substitution data is pointed. It can keep the recent access bit where as for the aforementioned block substitution controller, that the block location which corresponds recently is accessed the aforementioned block location part vis-a-vis at least respectively, shows high and is related how. In addition, the aforementioned block substitution controller, whether or not the recent access bit of specification, has shown the fact that the aforementioned qualified block location is recently accessed, can remember the aforementioned substitution data in the qualified block location which the aforementioned individual count value has pointed according to.
机译:高速缓冲存储器系统具有与块替换控制器(266)一起使用的高速缓冲存储器(269、16A,17A和18A)。前述高速缓冲存储器可以具有多个集合,其中每个具有多个块位置。前述块替换控制器可以保持对应于前述缓存存储器的每组的个体计数值。为了指出替换数据,上述个人计数值是在上述指定设置中限定块位置的同时。对于前述的块替换控制器,可以保持最近的访问位,其中,至少对应于最近访问的前述的块位置分别相对于前述的块位置部分被高显示,并且如何相关。另外,上述块替换控制器,无论规范的最近访问位是否已经表明最近访问了上述合格块位置的事实,都可以记住上述个体计数值的合格块位置中的上述替换数据。已经指出了。

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