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Operation mapping method to reconfigurable circuit, reconfigurable circuit, and data flow graph

机译:可重构电路的操作映射方法,可重构电路和数据流程图

摘要

PPROBLEM TO BE SOLVED: To provide an arithmetic mapping method to a reconfigurable circuit for reducing a circuit scale, and for shortening processing time and the reconfigurable circuit using the arithmetic mapping method. PSOLUTION: This arithmetic mapping method for mapping an expected operation function to a reconfigurable circuit equipped with an arithmetic part configured of a plurality of logic circuits capable of selectively executing a plurality of arithmetic logical operation functions and a connection part for holding a connection relation between the plurality of logic circuits comprises a number of valid bit decision step for deciding the number of valid bits input to the input of the expected operation function and a mapping step for mapping the expected operation function to the reconfigurable circuit based on the number of valid bits decided in the valid bit number decision step. Also, this arithmetic mapping method comprises a code decision step for deciding the code of the input of the expected operation function and a mapping step for mapping the expected operation function to the reconfigurable circuit based on the code decided by the code decision step. PCOPYRIGHT: (C)2007,JPO&INPIT
机译:

要解决的问题:为可重构电路提供算术映射方法,以减小电路规模,并缩短使用算术映射方法的处理时间和可重构电路。解决方案:该算术映射方法用于将期望的运算函数映射到可重构电路,该可重构电路配备有由能够选择性地执行多个算术逻辑运算功能的多个逻辑电路构成的算术部分和用于保持连接的连接部分。多个逻辑电路之间的关系包括:用于确定输入到期望运算函数的输入的有效位数的有效位数确定步骤;以及用于基于逻辑运算数将期望运算函数映射到可重构电路的映射步骤。在有效位数确定步骤中确定的有效位。而且,该算术映射方法包括:代码判定步骤,用于判定期望操作函数的输入的代码;以及映射步骤,用于基于由代码判定步骤所判定的代码,将期望操作函数映射至可重构电路。

版权:(C)2007,日本特许厅&INPIT

著录项

  • 公开/公告号JP4597075B2

    专利类型

  • 公开/公告日2010-12-15

    原文格式PDF

  • 申请/专利权人 三洋電機株式会社;

    申请/专利号JP20060063741

  • 发明设计人 岡田 誠;小曽根 真;

    申请日2006-03-09

  • 分类号G06F7;H03K19/173;

  • 国家 JP

  • 入库时间 2022-08-21 18:18:08

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