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MEMORY-CONTROLLER-PARALLELISM-AWARE SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS
MEMORY-CONTROLLER-PARALLELISM-AWARE SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS
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机译:多个存储器控制器的存储器-控制器-并行-AWARE调度
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摘要
Some embodiments of a processing system implement a memory-controller-parallelism-aware scheduling technique. In at least one embodiment of the invention, a method of operating a processing system includes scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor according to thread priority information associated with the plurality of threads. The thread priority information is based on a maximum of a plurality of local memory bandwidth usage indicators for each thread of the plurality of threads. Each of the plurality of local memory bandwidth usage indicators for each thread corresponds to a respective memory controller of a plurality of memory controllers.
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