An original processor uses addresses with a first length of n bits for addressing in a cyclical address space and a target processor uses addresses with a second length of m bits, where the second length m is greater than the first length n. In the original processor, distance values that lie between a lower value min and an upper value max are permissible for the base register-relative addressing. The supported address space on the original processor for the code to be emulated is limited in such a manner that the conversion of address operands as described in the following steps leads to semantically equivalent behavior on the target processor. A projected address on the target processor is initially determined by forming the sum of the content of the base register (R) and an offset (D) that is greater than or equal to a first offset (D1) of a base register-relative instruction and less than the difference (max−min), and projecting the sum onto a cyclical address space with addresses having a length of n bits. Addresses for converting the base register-relative instructions are determined from the calculated projected address and the respective distance values (D1, D2) of the instructions minus the offset D.
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