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Programming method to reduce gate coupling interference for non-volatile memory

机译:减少非易失性存储器的栅极耦合干扰的编程方法

摘要

A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level.
机译:描述了一种非易失性存储设备和编程过程,其通过鉴于在随后的编程中被编程的数据来调整编程的阈值电压电平,从而补偿对相邻的浮栅或非导电的浮置节点存储单元的阈值栅极电压的耦合效应。循环进入相邻的存储单元,从而耦合效应导致该单元具有所需的目标阈值电压。在本发明的一个实施例中,通过在给定要写入的数据/编程水平的情况下,通过将存储阵列的第一页的一个或多个存储单元的编程水平调整为更高或更低的阈值验证目标电压来补偿存储单元耦合。第二页的直接相邻的存储单元,使得第一页和第二页的直接相邻的存储单元之间的耦合使第一页的存储单元达到其最终目标编程级别。

著录项

  • 公开/公告号US8050096B2

    专利类型

  • 公开/公告日2011-11-01

    原文格式PDF

  • 申请/专利权人 SEIICHI ARITOME;

    申请/专利号US20100702688

  • 发明设计人 SEIICHI ARITOME;

    申请日2010-02-09

  • 分类号G11C16/04;

  • 国家 US

  • 入库时间 2022-08-21 18:10:31

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