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Failure Analysis Based on Time-Varying Failure Rates

机译:基于时变故障率的故障分析

摘要

Failure analysis method and apparatus using failure rate data in coordination with the power on hours to more efficiently resolve computer system failures without occupying system memory or processor bandwidth. In response to a system failure, a baseboard management controller (BMC) notes the time of failure and the elapsed operating time of system components. In response to a failure of the computer system, the BMC accesses industry standard failure rate data correlating the elapsed operating time with the probability of failure for each component. By cross-referencing the time of failure with the failure rate data, the BMC automatically determines the probability of failure of each component at the time of failure of the computer system. The BMC generates a component replacement list identifying the component that currently has the highest probability of failure.
机译:故障分析方法和装置使用故障率数据与开机时间配合使用,以更有效地解决计算机系统故障,而不占用系统内存或处理器带宽。响应系统故障,基板管理控制器(BMC)记录故障时间和系统组件的运行时间。响应计算机系统的故障,BMC访问行业标准的故障率数据,该数据将经过的工作时间与每个组件的故障概率相关联。通过将故障时间与故障率数据交叉引用,BMC在计算机系统故障时自动确定每个组件的故障概率。 BMC生成一个组件替换列表,该列表标识了当前故障可能性最高的组件。

著录项

  • 公开/公告号US2010313072A1

    专利类型

  • 公开/公告日2010-12-09

    原文格式PDF

  • 申请/专利权人 EDWARD S. SUFFERN;

    申请/专利号US20090477199

  • 发明设计人 EDWARD S. SUFFERN;

    申请日2009-06-03

  • 分类号G06F11/07;

  • 国家 US

  • 入库时间 2022-08-21 18:09:52

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