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Method for creating mask layout data, apparatus for creating mask layout data, and method for manufacturing semiconductor device

机译:用于创建掩模版图数据的方法,用于创建掩模版图数据的设备以及用于制造半导体器件的方法

摘要

According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length. Thereafter, the concentration of impurity introduced into a channel layer is set for each group, and thereby the gate length-threshold characteristics of a transistor are controlled. An overlapping area of a gate electrode and an element region of a certain group is extracted from mask layout data. The overlapping area is expanded to determine the shape of a mask used in injecting impurity in a channel layer. The data on the mask shape is then added to the mask layout data.
机译:根据为特定工厂设施创建的掩模布局数据,根据栅极长度将构成半导体器件的晶体管分为多个组。此后,为每组设置引入沟道层的杂质浓度,从而控制晶体管的栅极长度-阈值特性。从掩模布局数据中提取栅电极和特定组的元件区域的重叠区域。重叠区域被扩大以确定用于在沟道层中注入杂质的掩模的形状。然后,将遮罩形状上的数据添加到遮罩布局数据中。

著录项

  • 公开/公告号US7913195B2

    专利类型

  • 公开/公告日2011-03-22

    原文格式PDF

  • 申请/专利权人 YOSHIHIRO TAKAO;

    申请/专利号US20080026753

  • 发明设计人 YOSHIHIRO TAKAO;

    申请日2008-02-06

  • 分类号G06F17/50;G06F19/00;H01L21/00;

  • 国家 US

  • 入库时间 2022-08-21 18:08:24

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