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Formally deriving a minimal clock-gating scheme
Formally deriving a minimal clock-gating scheme
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机译:正式推导最小时钟门控方案
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摘要
The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.
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