MINIMIZING MEMORY BARRIERS WHEN ENFORCING STRONGLY-ORDERED REQUESTS IN WEAKLY-ORDERED PROCESSING SYSTEM

摘要

The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.