首页> 外国专利> SEMICONDUCTOR MEMORY DEVICE, CAPABLE OF PROPERLY SELECTING A FAST EXIT MODE AND A SLOW EXIT MODE, A MEMORY CONTROL PART THEREOF, AND AN INFORMATION PROCESSING SYSTEM THEREOF

SEMICONDUCTOR MEMORY DEVICE, CAPABLE OF PROPERLY SELECTING A FAST EXIT MODE AND A SLOW EXIT MODE, A MEMORY CONTROL PART THEREOF, AND AN INFORMATION PROCESSING SYSTEM THEREOF

机译:能够正确选择快速退出模式和慢速退出模式的半导体存储器,其存储器控制部及其信息处理系统

摘要

PURPOSE: A semiconductor memory device, a memory control part thereof, and an information processing system thereof are provided to reduce power consumption by using a selection signal which is inputted to a semiconductor memory device when a power-down command is generated.;CONSTITUTION: A memory cell array(70) comprises a plurality of memory cells. An output buffer(81) outputs read data, which is read from the memory cell array, to the outside. A DLL(Delay Locked Loop) circuit(23) controls the operation timing of the output buffer. A power-down control circuit(100) stops the operation of a predetermined internal circuit in response to the generation of a power-down command from the outside. A clock generating circuit(22) generates an internal clock.;COPYRIGHT KIPO 2011
机译:目的:提供一种半导体存储器件,其存储控制部件及其信息处理系统,以通过使用在产生掉电命令时输入到半导体存储器件的选择信号来降低功耗。存储单元阵列(70)包括多个存储单元。输出缓冲器(81)将从存储单元阵列读取的读取数据输出到外部。 DLL(延迟锁定环)电路(23)控制输出缓冲器的操作时序。断电控制电路(100)响应于来自外部的断电命令的产生而停止预定内部电路的操作。时钟产生电路(22)产生内部时钟。; COPYRIGHT KIPO 2011

著录项

  • 公开/公告号KR20100129219A

    专利类型

  • 公开/公告日2010-12-08

    原文格式PDF

  • 申请/专利权人 ELPIDA MEMORY INC.;

    申请/专利号KR20100050049

  • 发明设计人 FUJISAWA HIROKI;SATO TAKENORI;

    申请日2010-05-28

  • 分类号G11C11/4074;G11C11/407;G11C11/4076;G11C11/4093;

  • 国家 KR

  • 入库时间 2022-08-21 17:53:10

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