首页> 外国专利> SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME, CAPABLE OF REDUCING THE CONTACT RESISTANCE OF A LANDING PLUG BY REDUCING THE ASPECT RATIO OF A LANDING PLUG

SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME, CAPABLE OF REDUCING THE CONTACT RESISTANCE OF A LANDING PLUG BY REDUCING THE ASPECT RATIO OF A LANDING PLUG

机译:半导体装置和形成该半导体装置的方法,该方法能够通过减小落锤的纵横比来减小落锤的接触电阻

摘要

PURPOSE: A semiconductor device and a method for forming the same are provided to prevent a self-align contact fail and a gate induced drain leakage phenomenon by forming a dummy gate on the upper side of a buried gate as an etching barrier.;CONSTITUTION: An element isolation film defines an active region(12) on a semiconductor substrate. A plurality of buried gates(20) is formed to cross a plurality of active regions in a transversal direction. A dummy gate(30) is formed on the upper side of the buried gates. A landing plug(46) is formed on the junction region of the semiconductor substrate. An interlayer insulating film(42) is formed on the upper side of the semiconductor substrate.;COPYRIGHT KIPO 2011
机译:目的:提供一种半导体器件及其形成方法,以通过在掩埋栅的上侧形成虚拟栅作为蚀刻阻挡层来防止自对准接触失败和栅引起的漏漏现象。元件隔离膜在半导体衬底上限定有源区(12)。形成多个掩埋栅(20)以在横向上与多个有源区交叉。伪栅极(30)形成在掩埋栅极的上侧。在半导体基板的接合区域上形成有接地栓(46)。在半导体衬底的上侧形成层间绝缘膜(42)。COPYRIGHTKIPO 2011

著录项

  • 公开/公告号KR20110011430A

    专利类型

  • 公开/公告日2011-02-08

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20090069072

  • 发明设计人 HONG SUNG PYO;

    申请日2009-07-28

  • 分类号H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 17:52:35

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