METHOD AND SYSTEM TO INDICATE AN EXCEPTION­TRIGGERING PAGE WITHIN A MICROPROCESSOR

摘要

The present invention is a software-managed page is any page in the table, for example within a microprocessor, such as digital signal processors Displays whether the triggering exception to methods and systems for the will of software-managed translation lookaside buffer (TLB: translation look-aside buffer) modules such as fetch command (fetch instruction) and the same long instruction word (VLIW: Very Long Instruction Word ) receive a virtual address generated by the command in the packet, and compares the virtual address with each stored TLB entry. If the match (match) is present, TLB module outputs a physical address that is mapped corresponding to the command. Relatively not, if there is VLIW packet over two pages (here, the first page is provided as TLB entries in the TLB module and the second page is stored in the TLB entry from a sewing machine (missing)), the data field of the control register The bits in the display (indication bit) is set to identify the TLB miss exception for the software managing unit. Software management unit is adapted to retrieve information from a display bit register, using the information to retrieve the missing bit display (missing) page information software-managed page table within the page table look-up is performed (look-up). Next, the sewing machine page information is recorded in the new TLB entry in the TLB module to the next virtual address translation and execution of the command of the packet.