A Novel Monolithic Combo Nonvolatile Memory Allowing Byte Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout

摘要

The non-volatile memory array is a flash memory cell having a single transistor and two-transistor EEPROM memory cell that can be integrated on the same substrate. The non-volatile memory cell having a floating gate having a low coupling factor for the small memory cell. The floating gate is disposed above the tunneling dielectric layer, aligned with the edge of the source region and the drain region and has a width defined by the edge width of the source and drain. Floating gate and a control gate is capable of scaling of the nonvolatile memory cell, since it has a relatively low bonding ratio of 50% or less. Non-volatile memory cell is programmed by channel hot electrons at a relatively high voltage to the Fowler Nordheim tunneling program is erased. ; Bonding ratio, floating gate, select gating transistor, the erase / program