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SELF-CHECKING MODULAR PARAMETER CALCULATOR FOR SYSTEMS OF LOGICAL FUNCTIONS

机译:逻辑功能系统的自检模块参数计算器

摘要

Self-checking the modular calculator system logic functions, comprising a block conjunctions, whose inputs are the inputs of the device for supplying n Boolean variables, the outputs of which are connected to the first block memory for storing coefficients of a first polynomial redundant modular numerical normal form, a first adder, characterized in that it additionally administered second memory block, the inputs of which are connected with conjunctions unit outputs, wherein the second memory unit for storing coefficients W cerned polynomial modular redundant numerical normal shape, outputs of the first storage unit are connected to inputs of the first adder, the outputs of which are connected to the (s + 1) th, (s + 2) th, ..., (d + s) -th inputs (d - the number of realizable Boolean functions constituting data bits divisible AN-code, s - number of redundant Boolean functions corresponding redundant digits separable AN-code) block computing residue modulo and data inputs of the memory register, the outputs of which are the outputs of issuing values ​​apparatus d Boolean function s, the outputs of the second memory block are connected to inputs of the second adder, the outputs of which are connected to the 1st, 2nd, ..., s-th inputs of the modulo remainder calculation unit, the outputs of which are connected to the inputs of OR-NO element whose output is connected to a first input aND gate, a second input coupled to an input clock supply device, and an output connected to the clock terminal of register memory.
机译:自检模块化计算器系统的逻辑功能,包括一个块连接,其输入是用于提供n个布尔变量的设备的输入,其输出连接到第一块存储器,用于存储第一多项式冗余模块化数值的系数正常形式,是第一加法器,其特征在于,它另外管理第二存储块,其输入与连词单元输出连接,其中第二存储单元用于存储系数W,多项式,模数冗余,数字正常形状,第一存储的输出单元连接到第一个加法器的输入,第一个加法器的输出连接到第(s + 1),(s + 2),...,(d + s)-个输入(d-可实现的布尔函数,构成数据位可分割的AN代码,s-冗余布尔函数的数量,对应于冗余数字(可分离的AN代码),用于计算存储器的余数模和数据输入y寄存器,其输出是发行值设备d布尔函数s的输出,第二个存储块的输出连接到第二个加法器的输入,第二个加法器的输出连接到1st,2nd,....模余数计算单元的第..个输入,其输出连接到OR-NO元素的输入,其输出连接到第一输入与非门,第二输入耦合到输入时钟供应设备,输出连接到寄存器存储器的时钟端子。

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