Method for manufacturing a memory cell configuration with a corrugated bit - arrangement and the corresponding memory cell configuration with a corrugated bit - arrangement

摘要

Method for manufacturing a memory cell configuration with a corrugated bit - arrangement comprising the steps of:Forming a plurality of active regions (aa1 – aa3) along a first direction (i) in a semiconductor substrate (1), which of isolation trenches (10a, d) are surrounded on all sides;Forming a plurality of parallel buried word lines (wl1 – wl4) along a second direction (x) in the semiconductor substrate (1), which is determined by the active regions (aa1 – aa3), whereby in each case two from one another and from the isolation trenches (10a, d) spaced apart from the buried word lines (wl3, wl4) by means of a respective active region (aa1 – aa3) and wherein said buried word lines (wl1 – wl4) by means of a gate dielectric layer (30) of a channel region (k) in the semiconductor substrate (1) are isolated;Forming a respective source region (s) between the two word lines (wl3, wl4) and a first and second said drain region (d1, d2) between in each case one of the two word lines (wl3, wl4) and an adjacent insulating trench (10a, 10b) in each active region (aa1 – aa3);Forming a plurality of parallel bit lines (bl1 – bl4) with a corrugated bit - arrangement along..