Electrically erasable synchronous frequency thyristor has two gates for passage control and deletion of electrical current flow between anode and cathode

摘要

The electrically erasable synchronous frequency thyristor has two gates, particularly gate 1 (G1) and gate 2 (G2) for the passage control and deletion of the electrical current flow between anode (A) and cathode (K). A controllable parasitic thyristor is formed between two PNP transistors. An avoidance of advance control is obtained between anode and cathode by leakage or residual current of the fed back complementary transistors. An independent claim is also included for an electronic wiring symbol.