首页> 外国专利> Semiconductor arrangement manufacturing method, involves partially optimizing deceleration oxide and scattering oxide such that photons are raised to surface of guard ring and silicide is limited in guard ring area

Semiconductor arrangement manufacturing method, involves partially optimizing deceleration oxide and scattering oxide such that photons are raised to surface of guard ring and silicide is limited in guard ring area

机译:半导体装置的制造方法,包括部分优化减速氧化物和散射氧化物,使得光子上升到保护环的表面,并且硅化物被限制在保护环区域

摘要

The method involves partially optimizing deceleration oxide (41) and scattering oxide before producing surface-proximate areas with two different types of dopants such that photons are raised to a surface of a guard ring and silicide is limited in a guard ring area. A doped epitaxial layer is applied at a highly doped substrate, where the epitaxial layer and the substrate are doped with similar dopants. Thickness of a protective and brake oxide layer of a schottky diode of a semiconductor arrangement is set as 50 nanometers for implantation energy of 150 kilo electron volt.
机译:该方法包括在产生具有两种不同类型的掺杂剂的接近表面的区域之前部分优化减速氧化物(41)和散射氧化物,使得光子升高到保护环的表面并且硅化物被限制在保护环区域中。将掺杂的外延层施加在高度掺杂的衬底上,其中,外延层和衬底被掺杂有相似的掺杂剂。对于150千克电子伏特的注入能量,将半导体装置的肖特基二极管的保护和制动氧化物层的厚度设置为50纳米。

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