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Semiconductor arrangement manufacturing method, involves partially optimizing deceleration oxide and scattering oxide such that photons are raised to surface of guard ring and silicide is limited in guard ring area
Semiconductor arrangement manufacturing method, involves partially optimizing deceleration oxide and scattering oxide such that photons are raised to surface of guard ring and silicide is limited in guard ring area
The method involves partially optimizing deceleration oxide (41) and scattering oxide before producing surface-proximate areas with two different types of dopants such that photons are raised to a surface of a guard ring and silicide is limited in a guard ring area. A doped epitaxial layer is applied at a highly doped substrate, where the epitaxial layer and the substrate are doped with similar dopants. Thickness of a protective and brake oxide layer of a schottky diode of a semiconductor arrangement is set as 50 nanometers for implantation energy of 150 kilo electron volt.
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