CLOCK FREQUENCY CONTROL CIRCUIT AND CLOCK FREQUENCY CONTROL METHOD

摘要

PROBLEM TO BE SOLVED: To implement a PLL circuit for generating a signal with a slight frequency change while relatively reducing a signal frequency division rate and suppressing an increase in phase noise.;SOLUTION: A clock frequency control circuit includes: a voltage-controlled oscillator having an output frequency varying with voltage input from a correlation circuit for controlling the output frequency by controlling a predetermined voltage; a first frequency division circuit for dividing the output of the voltage-controlled oscillator; a second frequency division circuit for dividing an externally input reference frequency; a phase comparator for outputting a pulse depending on the phases of the outputs of the first frequency division circuit and second frequency division circuit; and a low pass filter for extracting low frequency components from the output of the phase comparator for input to the voltage-controlled oscillator.;COPYRIGHT: (C)2012,JPO&INPIT