首页> 外国专利> Integrated circuit design support apparatus, integrated circuit design support method, integrated circuit design support program, and recording medium on which this program is recorded

Integrated circuit design support apparatus, integrated circuit design support method, integrated circuit design support program, and recording medium on which this program is recorded

机译:集成电路设计支持装置,集成电路设计支持方法,集成电路设计支持程序以及记录该程序的记录介质

摘要

Provided is an integrated circuit design support apparatus capable of estimating the optimal wiring length and wiring congestion at the stage of implementing a logical design of an integrated circuit, thereby preventing the do-over of the logical design or functional design caused by a wiring delay that is discovered at a packaging design stage, and shortening the time required for designing the integrated circuit. The present invention is able to accurately estimate the wiring length between the modules and the wiring congestion in the modules at the stage of implementing the logical design of the integrated circuit, and reflect the logical design result of the integrated circuit in the packaging design of the integrated circuit.
机译:提供一种集成电路设计支持装置,该装置能够在实施集成电路的逻辑设计的阶段估计最佳布线长度和布线拥塞,从而防止由于布线延迟而导致的逻辑设计或功能设计的重复。在封装设计阶段就发现了这种材料,从而缩短了设计集成电路所需的时间。本发明能够在实施集成电路的逻辑设计的阶段准确地估计模块之间的布线长度和模块中的布线拥塞,并在集成电路的封装设计中反映集成电路的逻辑设计结果。集成电路。

著录项

  • 公开/公告号JP5060991B2

    专利类型

  • 公开/公告日2012-10-31

    原文格式PDF

  • 申请/专利权人 株式会社日立製作所;

    申请/专利号JP20080042083

  • 发明设计人 坂 尋正;

    申请日2008-02-22

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 17:40:03

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